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ds07-08103-1e fujitsu semiconductor data sheet family fr400 series vliw embedded microprocessor mb93423 description this specifications describe the implementation of t he mb93423, incorporating a processor core (fr403-soc) designed for embedded applications, whic h is based on a vliw (very long inst ruction word) architecture (the fr-v architecture) . this processor can issue the integer operation instruction, media instruction, and branch instruction, up to two instructions, in units called the ?vliw instruction? on a cycle-by-cycle basis. also, the processor incorporates the following resour ces : sdram controller (sdramc) , interrupt controller (irc) , dma controller (dmac) , asynchronous transfer module (uart) , timer/counter (timer/counter) , general-purpose i/o (gpio) , video display controller (v dc) , video capture controller (vcc) , scaler, audio interface, serial interface (i 2 c*) , usb interface, and memory stick in terface. the vliw instruction and these resources achieve an excellent cost performance in a complex of high-performance general-purpose processing and media processing, such as multif unction printers, digital cameras, and portable information terminals. * : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specific ation as defined by philips. pac k ag e 337-ball plastic pfbga (bga-337p-m03)
mb93423 2 features cpu core 2-way 240 mhz or 266 mhz vliw processor core peak performance 480 mips (integer operation performance) at 240 mhz 1920 mops + 240 mips (media operation performance) at 240 mhz 532 mips (integer operation performance) at 266 mhz 2128 mops + 266 mips (media operation performance) at 266 mhz 64 32-bit registers (32gr + 32fr) cache instruction cache : 8 kbyte (2way) , line size 32 byte data cache : 8 kbyte (2way) , line size 32 byte cache line replace algorithm : lru lnstruction cache preload instruction (icpl) , data cache preload instruction (dcpl) support cache lock support of both instruction and data for each line non-blocking cache (data cache) store buffer : 64-byte (data cache) sdram interface sdram in accordance with the pc100 or pc133 standard can be connected. changeable 32/16-bit data bus four cs (2 support only registered-dimm) dmac four channels (dual address mode) data transfer size is select ed from 1, 2, 4 and 32 bytes maximum 4g-byte data transfer priority is fixed or round robin. four external request demand signals (dreq#[3 : 0]) 32-byte fifo is built in each dma channel address update select from increment, holding and decrement circular addressing when the transfer byte count reaches the specified value, the transfer address is reset to the initial value and transfer continues. when internal request is specified while circular addressi ng is specified, the internal request will be ignored. 2d addressing when the transfer byte count reaches the specified value, ?initial value + ap value? is set to transfer address and transfer continues. local bus interface 24-bit address / 16-bit or 8-bit data can directly connect sram, rom, etc. the programmable address decoder is built into, and maximum 4 chip select pins are equipped with. can specify the bus width by each chip select. (select from 16 bits or 8 bits) the programmable wait state generator is built into. interrupt controller maximum 4 external interrupt factors are input (irq3-0) / 11 internal interrupt factors are input : (dma = 4, timer = 3, uart = 2 and error response = 2) interrupt factors are mapped in 15 levels of interrupt requests. (continued)
mb93423 3 uart 16550 subsets 2 channels of uart are equipped. prescaler to generate baud rate is built into. modem control signal external pins (rts #/cts#) are equipped (to only channel 0) . timer 8254 subsets 3 channels of 16-bit timer are equipped. supports mode 0 (terminal count inte rrupt) , mode 2 (rate generator) , mode 4 (software trigger strobe) , and mode 5 (hardware trigger strobe) . no other mode is supported. supports the binary counter. (bcd counter is not supported.) one channel of prescaler is mounted on the former steps in the timer block. gpio 16-bit general-purpose i/o port is equipped with. (other peripheral functions and i/o pins are shared.) jtag supports the ieee1149.1 jtag boundary scan function. video output progressive or interlaced scan method 320 to 1920 pixels horizontal resolution , 240 to 1200 pixels vertical resolution supports 4 : 2 : 2 ycbcr 8 bits (time-shared; cbycry; conforms to bt.656) , 4 : 2 : 2 ycbcr 16 bits (cb and cr output time-shared; cb precedes cr) , 4 : 2 : 2 yc bcr 24 bits (cb and cr output concurrently; 2 clocks output) , 4 : 4 : 4 rgb 24 bits for output format supports 4 : 2 : 2 ycbcr 16 bits (cb and cr time-shared; cb precedes cr) , 4 : 4 : 4 rgb 24 bits (no filler byte) for input data hardware cursor : 1 piece (32 32; 2 colors + transparent color) video input progressive or interlaced scan method 320 to 1920 pixels horizontal resolution , 240 to 1200 pixels vertical resolution supports 4 : 2 : 2 ycbcr 8 bits (time-shared; cbycry; conforms to bt.656) , 4 : 2 : 2 ycbcr 16 bits (cb and cr output time-shared; cb precedes cr) , 4 : 2 : 2 yc bcr 24 bits (cb and cr output concurrently; 2 clocks output) , 4 : 4 : 4 rgb 24 bits for input format supports 4 : 2 : 2 ycbcr 16 bits (cb and cr time-shared; cb precedes cr) , 4 : 4 : 4 rgb 24 bits (no filler byte) for output data hardware cursor : 1 piece (32 32; 2 colors + transparent color) scaler maximum pixel count in horizontal direction for input image size : 1920 (brightness component) maximum pixel count in vertical di rection for input image size : 768 maximum pixel count in horizontal direction fo r output image size : 3 60 (brightness component) maximum pixel count in vertical direction for output image size : 288 audio output this is an interface supporting the 3-wire serial (supporting i 2 s which is msb-justified) and the pcm highway. maximum : 32 bits/sample (i 2 s which is msb-justified) fixed at 8 bits/sample (pcm highway) depends on frequency of supplied clock (either of the follo wing is supplied from outs ide : 256/384/512/768 fs.) (continued)
mb93423 4 (continued) audio input this is an interface supporting the 3-wire serial (supporting i 2 s which is msb-justified) and the pcm highway. input data is arranged in the front-just ified format (starting with msb) . maximum : 32 bits/sample (i 2 s which is msb-justified) fixed at 8 bits/sample (pcm highway) depends on frequency of supplied clock (either of the follo wing is supplied from outside : 256/384/512/768 fs.) usb compliant with usb 2.0 fs function. v bus and isochronous transfer are not supported. i 2 c standard mode (100 kbps) and the fast mode (400 kbps) are supported. memory stick compliant with memory stick standard format specification ver1.4. memory stick pro and memory stick duo are suppo rted. (however, excluded magic gate function.) av gpio 32 bits (correspond to the pins shared with other functions.) clock control clock supply can be turned on/off for each unit. recommended operation condition power supply voltage : externally 3.3 v 0.15 v, internally 1.8 v 0.1 v operating temperature range from 0 c to + 70 c product lineup these specifications have indicated two kinds of following products. part number mb93423bgl-ge1 MB93423-26BGL-GE1 core frequency 240 mhz 266 mhz voltage external / internal 3.3 v 0.15 v / 1.8 v 0.1 v 3.3 v 0.15 v / 1.8 v 0.1v ta 0 c to + 70 c package (code) pfbga337 (bga-337p-m03) thermal resistance rth (ja) 45 c/w (0 m/s) remarks lead-free solder ball
mb93423 5 pin assignment 49 pins from k10 to t16 are for thermal. connect them to vss. index 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 74 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 48 75 164 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 140 47 300 223 138 45 77 166 247 320 78 167 248 321 299 222 137 44 79 168 249 322 298 221 136 43 297 220 135 42 80 169 250 323 81 170 251 324 296 219 134 41 82 171 252 325 295 218 133 40 83 172 253 326 294 217 132 39 84 173 254 327 293 216 131 38 85 174 255 328 292 215 130 37 86 175 256 329 291 214 129 36 87 176 257 330 290 213 128 35 88 177 258 331 289 212 127 34 89 178 259 332 288 211 126 33 90 179 260 333 287 210 125 32 91 180 261 334 286 209 124 31 92 181 262 335 285 208 123 30 93 182 263 336 337 284 207 122 29 94 183 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 206 121 28 95 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 120 27 76 165 246 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 224 139 46 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 26 25 24 23 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 22 12 a b c d e f g h j k l m n p r t u v w y a a a b a c a d a e (bga-337p-m03) (top-view)
mb93423 6 (continued) pin no. position pin name pin no. position pin name pin no. position pin name 1 a1 n.c. 36 ae12 vss 71 c25 ddq[31] 2 b1 clkin 37 ae13 n.c. 72 b25 vde 3 c1 vddp 38 ae14 n.c. 73 a25 n.c. 4 d1 bs# 39 ae15 tout[0] 74 a24 mtestmode 5 e1 we# 40 ae16 rxd[1] 75 a23 rstout# 6 f1 cs#[3] 41 ae17 irq#[1] 76 a22 cmode[1] 7 g1 vcr[7] 42 ae18 vde 77 a21 testmode 8 h1 vcr[3] 43 ae19 dreq#[3] 78 a20 tdo 9 j1 vss 44 ae20 vdd 79 a19 tdi 10 k1 vcb[5] 45 ae21 vde 80 a18 erst# 11 l1 vcb[1] 46 ae22 ddq[5] 81 a17 vdd 12 m1 vss 47 ae23 ddq[6] 82 a16 d[19] 13 n1 vde 48 ae24 vde 83 a15 d[21] 14 p1 vdd 49 ae25 n.c. 84 a14 d[25] 15 r1 vcg[3] 50 ad25 ddq[9] 85 a13 d[26] 16 t1 vcg[1] 51 ac25 ddq[8] 86 a12 d[28] 17 u1 vdr[5] 52 ab25 ddq[12] 87 a11 be[0] 18 v1 vss 53 aa25 ddq[14] 88 a10 vde 19 w1 vdb[7] 54 y25 ddqm[0] 89 a9 a[4] 20 y1 vdb[3] 55 w25 vde 90 a8 vss 21 aa1 vdb[0] 56 v25 dras# 91 a7 a[10] 22 ab1 vss 57 u25 vss 92 a6 a[14] 23 ac1 vdclkout 58 t25 da[5] 93 a5 a[16] 24 ad1 vde 59 r25 vss 94 a4 a[20] 25 ae1 n.c. 60 p25 dclkfb 95 a3 a[21] 26 ae2 vdg[5] 61 n25 vss 96 a2 vde 27 ae3 vdg[6] 62 m25 da[10] 97 b2 a[22] 28 ae4 vde 63 l25 dba[1] 98 c2 a[23] 29 ae5 vdg[1] 64 k25 vss 99 d2 vss 30 ae6 sdi 65 j25 ddq[16] 100 e2 rdy# 31 ae7 vss 66 h25 vde 101 f2 vss 32 ae8 lrcki 67 g25 ddq[22] 102 g2 cs#[1] 33 ae9 sda[0] 68 f25 vde 103 h2 vcr[5] 34 ae10 msins 69 e25 ddq[28] 104 j2 vcr[1] 35 ae11 msdio[2] 70 d25 ddq[30] 105 k2 vcb[7]
mb93423 7 (continued) pin no. position pin name pin no. position pin name pin no. position pin name 106 l2 vcb[3] 141 ad24 ddq[7] 176 b11 be[2] 107 m2 vchsync 142 ac24 ddq[11] 177 b10 a[2] 108 n2 vss 143 ab24 ddq[10] 178 b9 a[6] 109 p2 vcg[5] 144 aa24 vss 179 b8 a[8] 110 r2 vss 145 y24 dwe# 180 b7 a[12] 111 t2 vdr[7] 146 w24 dcs#[0] 181 b6 vdd 112 u2 vdr[3] 147 v24 dcs#[2] 182 b5 a[18] 113 v2 vdr[1] 148 u24 da[1] 183 b4 a[19] 114 w2 vdb[5] 149 t24 da[3] 184 b3 n.c. 115 y2 vdb[2] 150 r24 da[7] 185 c3 vdd 116 aa2 vdvsync 151 p24 vss 186 d3 n.c. 117 ab2 enable 152 n24 da[8] 187 e3 rd# 118 ac2 n.c. 153 m24 vde 188 f3 err# 119 ad2 vdg[7] 154 l24 da[12] 189 g3 dir 120 ad3 vdg[3] 155 k24 ddqm[2] 190 h3 vde 121 ad4 vdg[4] 156 j24 ddq[18] 191 j3 vcr[6] 122 ad5 vss 157 h24 ddq[20] 192 k3 vcr[0] 123 ad6 topfield 158 g24 ddq[24] 193 l3 vcb[4] 124 ad7 bcki 159 f24 ddq[26] 194 m3 vcvsync 125 ad8 lrcko 160 e24 vss 195 n3 vcdclkin 126 ad9 scl[0] 161 d24 vdd 196 p3 vcg[4] 127 ad10 vde 162 c24 n.c. 197 r3 vcg[0] 128 ad11 msdio 163 b24 cpuhold 198 t3 vdr[2] 129 ad12 vdd 164 b23 cmode[2] 199 u3 vdb[6] 130 ad13 n.c. 165 b22 cmode[3] 200 v3 vdhsync 131 ad14 uscki 166 b21 ramboot# 201 w3 vdr[0] 132 ad15 rxd[0] 167 b20 tdc 202 y3 vdd 133 ad16 txd[1] 168 b19 tck 203 aa3 n.c. 134 ad17 irq#[3] 169 b18 ecv 204 ab3 vss 135 ad18 dreq#[1] 170 b17 vss 205 ac3 vdd 136 ad19 msdirp# 171 b16 d[17] 206 ac4 n.c. 137 ad20 ddq[1] 172 b15 vss 207 ac5 vdg[2] 138 ad21 ddq[3] 173 b14 d[23] 208 ac6 vdg[0] 139 ad22 ddq[4] 174 b13 vss 209 ac7 vdpclkin 140 ad23 n.c. 175 b12 d[30] 210 ac8 disable
mb93423 8 (continued) pin no. position pin name pin no. position pin name pin no. position pin name 211 ac9 sdo 246 c22 n.c. 281 y4 vdb[4] 212 ac10 sda[1] 247 c21 prst# 282 aa4 vdb[1] 213 ac11 msbs 248 c20 vss 283 ab4 vss 214 ac12 msclk 249 c19 cmode[0] 284 ab5 fscki 215 ac13 udp 250 c18 vde 285 ab6 vdde 216 ac14 vss 251 c17 vss 286 ab7 bcko 217 ac15 txd[0] 252 c16 eclk 287 ab8 scl[1] 218 ac16 vss 253 c15 d[20] 288 ab9 vss 219 ac17 msdirs# 254 c14 d[24] 289 ab10 xmscki 220 ac18 ddq[2] 255 c13 d[27] 290 ab11 msdio[1] 221 ac19 dreq#[2] 256 c12 d[31] 291 ab12 msdio[3] 222 ac20 ddq[0] 257 c11 be[3] 292 ab13 udm 223 ac21 n.c. 258 c10 a[7] 293 ab14 vde 224 ac22 vss 259 c9 a[11] 294 ab15 tout[1] 225 ac23 vdd 260 c8 a[17] 295 ab16 vdd 226 ab23 n.c. 261 c7 a[9] 296 ab17 irq#[0] 227 aa23 vde 262 c6 vss 297 ab18 irq#[2] 228 y23 ddq[15] 263 c5 n.c. 298 ab19 dreq#[0] 229 w23 ddq[13] 264 c4 vss 299 ab20 vss 230 v23 dcas# 265 d4 vss 300 ab21 vss 231 u23 dcs#[1] 266 e4 cs#[2] 301 ab22 vss 232 t23 da[2] 267 f4 cs#[0] 302 aa22 ddqm[1] 233 r23 da[6] 268 g4 vcr[4] 303 y22 vss 234 p23 vddp 269 h4 vcr[2] 304 w22 dcs#[3] 235 n23 vdd 270 j4 vde 305 v22 da[0] 236 m23 dba[0] 271 k4 vcb[6] 306 u22 vde 237 l23 vde 272 l4 vcb[2] 307 t22 da[4] 238 k23 vss 273 m4 vcb[0] 308 r22 vde 239 j23 ddq[23] 274 n4 vcg[7] 309 p22 dclk 240 h23 ddq[29] 275 p4 vcg[6] 310 n22 da[9] 241 g23 ddq[21] 276 r4 vcg[2] 311 m22 vss 242 f23 ddq[25] 277 t4 vde 312 l22 da[11] 243 e23 n.c. 278 u4 vdr[6] 313 k22 dcke 244 d23 vss 279 v4 vdr[4] 314 j22 ddqm[3] 245 c23 vdd 280 w4 vde 315 h22 ddq[17]
mb93423 9 (continued) note : the power supply pins are classified as follow. vdd pin is the internal power supply pin. vddp pin is the analog power supply pin of pll. vde pin is the external power supply pin. vss pin is the ground pin (0 v). pin no. position pin name 316 g22 ddq[19] 317 f22 vss 318 e22 ddq[27] 319 d22 vss 320 d21 trst# 321 d20 tms 322 d19 hrst# 323 d18 ed 324 d17 d[16] 325 d16 d[18] 326 d15 vde 327 d14 d[22] 328 d13 vde 329 d12 d[29] 330 d11 be[1] 331 d10 vss 332 d9 a[3] 333 d8 a[5] 334 d7 vde 335 d6 a[13] 336 d5 a[15] 337 e5 n.c.
mb93423 10 pin description 1. format this section explains the pin functions of this lsi chip. the pin function list is in the format shown below : pin name : indicates name of external pin if several signals share the same pin, t he names are separated by a slash (/) . ?xx#? in a signal line name indicates ?active low?. direction : indicates i/o of signal with reference to lsi chip input : indicates pin for input signal to lsi chip output : indicates pin for output signal from lsi chip input/output : indicates pin for bidirectional signal type : indicates pin input/output circuit type each symbol has the following meaning : note : explains outline of functi on and relationship with other pins bs : indicates whether the targ et of boundary-scan or not. pin no. pin name direction type bs description symbol description sd solid drive type of output pin. normal output. the pin never becomes high impedance. ts tri - state type of output or input/output pin. the pin may become high impedance. pu pull - up type of input pin or input/output pin. a pu ll-up resistor is built into the circuit. pd pull - down type of input pin or input/output pin. a pu ll-down resistor is built into the circuit. od open - drain type of output pin. the pi n may become high impedance.
mb93423 11 2. local bus interface (continued) pin no. pin name direction type bs description pfbga 98 97 95 94 183 182 260 93 336 92 335 180 259 91 261 179 258 178 333 89 332 177 a[23] a[22] a[21] a[20] a[19] a[18] a[17] a[16] a[15] a[14] a[13] a[12] a[11] a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] output ts yes address a word address is output. when the local bus is released , these pins become input. 256 175 329 86 255 85 84 254 173 327 83 253 82 325 171 324 d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] input/ output ts yes data this is the data bus; d[31] is msb. when connecting a 16-bit slave device to this signal, con- nect it to d[31 : 16] (higher) . when connecting a 8-bit slave device to this signal, con- nect it to d[31 : 24] (higher) . 4bs#outputtsyes bus cycle start this is asserted for only 1 clkin cycle at the beginning of a bus cycle to indicate the start of the bus cycle. this pin becomes input w hen the bus is released.
mb93423 12 (continued) pin no. pin name direction type bs description pfbga 87 330 176 257 be[0] / be#[0] be[1] / be#[1] be[2] / be#[2] be[3] / be#[3] output ts yes byte enable this specifies byte lanes for data transfer. be [0 : 1] is used to access a 16-bit slave device; the cor- respondence between this si gnal and the data bus is shown below : be[0] d [31 : 24] (higher byte) be[1] d [23 : 16] (lower byte) be [2] is used to access halfword address. be [2] a[1] be [0] is used to access a 8-bit slave device; the corre- spondence between this signal and th e data bus is shown below : be [0] d [31 : 24] be [2 : 3] is used to access byte address. be [2] a[1] be [3] a[0] these pins become input when t he bus is released. to ac- cess this lsi as the slave device when this bus is released, it must be treated as a 32-bit slave device. 187 rd# output ts yes read this pin is asserted during t he second or later clkin cy- cles of read local bus cycles. this pin becomes high impedance when the local bus is re- leased. 5 we# output ts yes write enable this pin is asserted during a write cycles. it can be used as a strobe pulse for write data. this pin becomes high impe dance when the bus is re- leased. 189 dir output ts yes direction indicates transfer direction of d[31 : 16] pins l : input (read) , h : output (write) this pin becomes input when th e bus is released. this lsi determines whether the local bus cycles that performed by external devices are reads or writes, based on the dir sig- nal. this pin becomes ?l? when bus is idle. 100 rdy# input ? yes ready the bus cycle completion notice from the slave device is input. the value of rdy# is reflected to lcr0.rc at power-on re- set. 188 err# input ? yes error this is sampled at the end of th e bus cycle; the error notice is input from the slave device to this pin. this pin is ignored when the bus is released.
mb93423 13 (continued) pin no. pin name direction type bs description pfbga 6 266 102 267 cs#[3] cs#[2] cs#[1] cs#[0] output sd yes chip select this signal selects slave device under control of mb93423. the corresponding address is determined from the set- tings of the programmable address decoder built into mb93423. connect the boot rom to the cs#[0] pin.
mb93423 14 3. sdram interface (continued) pin no. pin name direction type bs description pfbga 304 147 231 146 dcs#[3] dcs#[2] dcs#[1] dcs#[0] output sd yes chip select this signal is determined by programmable address de- coder build into mb93423. dc s#[2] and dcs#[3] are used to specify 168pin registered dimm. 63 236 dba[1] dba[0] output sd yes bank address the bank address is output. 154 312 62 310 152 150 233 58 307 149 232 148 305 da[12] da[11] da[10] da[9] da[8] da[7] da[6] da[5] da[4] da[3] da[2] da[1] da[0] output sd yes multiplexed address the address multiplexed for sdram is output. 56 dras# output sd yes row address strobe row address strobe signal to sdram. 230 dcas# output sd yes column address strobe column address strobe signal to sdram. 145 dwe# output sd yes write enable write enable signal to sdram. 313 dcke output sd yes clock enable clock enable signal to sdram. 54 302 155 314 ddqm[0] ddqm[1] ddqm[2] ddqm[3] output sd yes data mask these pins (signal) are combined with other signals to specify the byte lane to be written. at read, all the bits are driven low. the correspondence between this signal and the data bus when connecting 32-bit sdram is shown below : ddqm[0] ddq[31 : 24] ddqm[1] ddq[23 : 16] ddqm[2] ddq[15 : 8] ddqm[3] ddq[7 : 0] the correspondence between this signal and the data bus when connecting 16-bit sdram is shown below : ddqm[0] ddq[31 : 24] ddqm[1] ddq[23 : 16]
mb93423 15 (continued) pin no. pin name direction type bs description pfbga 71 70 240 69 318 159 242 158 239 67 241 157 316 156 315 65 228 53 229 52 142 143 50 51 141 47 46 139 138 220 137 222 ddq [31] ddq[30] ddq[29] ddq[28] ddq[27] ddq[26] ddq[25] ddq[24] ddq[23] ddq[22] ddq[21] ddq[20] ddq[19] ddq[18] ddq[17] ddq[16] ddq[15] ddq[14] ddq[13] ddq[12] ddq[11] ddq[10] ddq[9] ddq[8] ddq[7] ddq[6] ddq[5] ddq[4] ddq[3] ddq[2] ddq[1] ddq[0] input/ output ts yes data this signal is connected to the sdram data bus; ddq[31] is msb. when connecting 16-bit sdram, connect it to ddq[31 : 16] when the bus width is set to 16 bits by dcfg.bw, ddq[15 : 0] is fixed to the high-impedance state. 309 dclk output sd yes sdram clock this is the output of the cl ock signal supplied to sdram. the output is supplied when mb93423 is in self refresh mode. the output is halted while the pll is halted. the output is also halted during a power-on reset. 60 dclkfb input ? yes feedback for sdram clock to adjust the dclk phase, feedback input to the pll built into this lsi chip.
mb93423 16 4. general peripheral resource (continued) pin no. pin name direction type bs description pfbga 296 41 297 134 irq#[0] / pp[0] irq#[1] / pp[1] irq#[2] / pp[2] irq#[3] / pp[3] input/ output ts yes interrupt request 0 to 3 / gpio 0 to 3 these pins are used as the interrupt input and as a gen- eral-purpose i/o port (gpio) . 39 tout[0] / gate[0] / pp[4] input/ output ts yes timer ch 0 o utput / timer ch 0 gate / gpio 4 this pin is used as the timer ch 0 pin and as a general- purpose i/o port (gpio) . 294 tout[1] / gate[1] / pp[5] input/ output ts yes timer ch 1 output / timer ch 1 gate / gpio 5 this pin is used as the timer ch 1 pin and as a general- purpose i/o port (gpio) . 132 rxd[0] / pp[6] input/ output ts yes uart ch 0 receive data / gpio 6 this pin is used as the uart ch 0 receive data and as a general-purpose i/o port (gpio) . 217 txd[0] / pp[7] input/ output ts yes uart ch 0 transmit data / gpio 7 this pin is used as the uart ch 0 transmit data and as a general-purpose i/o port (gpio) . 219 msdirs# / pp[8] input/ output ts yes memory stick direction serial / gpio 8 [memory stick licensees] customers are advised to consult with our sales repre- sentatives, if you use ms interface. [non-licensees] this pin is used as a general-purpose input port (gpio) . the output mode must not be used. 136 msdirp# / pp[9] input/ output ts yes memory stick direction parallel / gpio 9 [memory stick licensees] customers are advised to consult with our sales repre- sentatives, if you use ms interface. [non-licensees] this pin is used as a general-purpose input port (gpio) . the output mode must not be used. 40 rxd[1] / pp[10] input/ output ts yes uart ch 1 receive data / gpio 10 this pin is used as the uart ch 1 receive data and as a general-purpose i/o port (gpio) . 133 txd[1] / pp[11] input/ output ts yes uart ch 1 transmit data / gpio 11 this pin is used as the uart ch 1 transmit data and as a general-purpose i/o port (gpio) . 298 dreq#[0] / pp[12] input/ output ts yes dmac ch 0 request / gpio 12 this pin is used as the uart ch 0 transfer request and as a general-purpose i/o port (gpio) . 135 dreq#[1] / pp[15] input/ output ts yes dmac ch 1 transfer request / gpio 15 this pin is used as the dm ac ch 1 transfer request and as a general-purpose i/o port (gpio) .
mb93423 17 (continued) 5. ice interface pin no. pin name direction type bs description pfbga 221 dreq#[2] / pp[18] input/ output ts yes dmac ch 2 transfer request / gpio 18 this pin is used as the dmac ch 2 transfer request and as a general-purpose i/o port (gpio) . 43 dreq#[3] / pp[19] input/ output ts yes dmac ch 3 transfer request / gpio 19 this pin is used as the dmac ch 3 transfer request and as a general-purpose i/o port (gpio) . pin no. pin name direction type bs description pfbga 80 erst# input pd yes esb reset for the printed circuit board using the ice, connect the connector intended for the ice to this pin; for the printed circuit board not using the ice, open this pin. 322 hrst# input ? yes hard reset this is the reset input dedica ted to the ice. this pin function is equivalent to reset by the debugger hard- ware reset command. reset by this pin will not reset debug related settings, so th is pin can be used for de- bugging the reset sequence, etc. when using this pin, connec t the reset switch signal to this pin; when not using this pi n, fix it to the high level. 169 ecv input pu yes esb command valid command valid signal for ice interface. for the printed circuit board using the ice, connect the connector intended for the ice to this pin; for the printed circuit board not using the ice, open this pin. 323 ed input/ output ts pd yes esb data data i/o signal for ice interface. for the printed circuit board using the ice, connect the connector intended for the ice to this pin; for the printed circuit board not using the ice, open this pin. 252 eclk output ts yes esb clock clock signal (output) for ice interface. for the printed circuit board using the ice, connect the connector intended for the ice to this pin; for the printed circuit board not using the ice, open this pin.
mb93423 18 6. reset 7. cpu status 8. clocks pin no. pin name direction type bs description pfbga 247 prst# input ? yes power - on reset this is the level trigger initialization signal. apply the low level to this pin for 16 clkin clock cycles or more. this pin is used to cause a power-on rese t; it initializes all registers and sequencers except cache and gr/fr. 75 rstout# output sd yes reset output this signal is asserted during a power-on reset. the power-on reset operation is prolonged in the lsi until the oscillation stabilization wait time for the internal pll has elapsed. consequently, us e this signal to detect that the power-on reset operation has been completed in the lsi. when hrst# is asserted when the ice used, this signal (rstout#) is asserted as in the power-on reset. 166 ramboot# input ? yes ram boot a software reset can be caused by applying a low level to this pin. when this signal and the prst # pin are asserted simulta- neously, the power-on reset operation is prefered. at a power-on reset, the level input to this pin is reflected in the sa bit of the register hsr0, and then the reset vector address is determined as shown below based on the sa bit. low level : 0x00000000 high level : 0xff000000 pin no. pin name direction type bs description pfbga 163 cpuhold output sd yes cpu hold signal indicating that cpu stops in hold state pin no. pin name direction type bs description pfbga 2 clkin input ? yes clock input external clock are input to this pin. 165 164 76 249 cmode[3] cmode[2] cmode[1] cmode[0] input ? yes clock mode determines operating frequency of each section in lsi
mb93423 19 9. jtag 10. test pin no. pin name direction type bs description pfbga 79 tdi input pu no test data input this is the test data input pin. this signal is sampled on the rising edge of tck. 78 tdo output ts no test data output this is the test data output pin. this drives active when the atp controller is the shift-ir or shift-dr state. this signal changes on the falling edge of tck. 321 tms input pu no test mode select this is the test mode select pin. this signal is sampled on the rising edge of tck. 168 tck input pu no test clock this is the test clock pin. 320 trst# input pu no test reset this is the tap controller asynchronous reset. this pin ini- tializes the tap controller when not using the jtag function on the printed circuit board, input the same signal as prst# to this pin. pin no. pin name direction type bs description pfbga 77 testmode input ? yes test mode input fix it at low level on the printed circuit board. 167 tdc input ? no test input fix it at low level on the printed circuit board. 74 mtestmode input ? yes mtest mode input fix it at low level on the printed circuit board.
mb93423 20 11. vdc (continued) pin no. pin name direction type bs description pfbga 111 278 17 279 112 198 113 201 vdr[7]/vdcr[7]/avpp[23] vdr[6]/vdcr[6]/avpp[22] vdr[5]/vdcr[5]/avpp[21] vdr[4]/vdcr[4]/avpp[20] vdr[3]/vdcr[3]/avpp[19] vdr[2]/vdcr[2]/avpp[18] vdr[1]/vdcr[1]/avpp[17] vdr[0]/vdcr[0]/avpp[16] input/ output ts yes r component output / c r component output / gpio these pins are display video data output pins. in the rgb mode, the red component is out- put. in the 24-bit yc mode, c r component is output. these pins are shared by gpio unit and set as gpio input setting after reset. 119 27 26 121 120 207 29 208 vdg[7]/vdy[7]/vdx[7] vdg[6]/vdy[6]/vdx[6] vdg[5]/vdy[5]/vdx[5] vdg[4]/vdy[4]/vdx[4] vdg[3]/vdy[3]/vdx[3] vdg[2]/vdy[2]/vdx[2] vdg[1]/vdy[1]/vdx[1] vdg[0]/vdy[0]/vdx[0] output ts yes g component output / y component output / yc multiplexed output these pins are display video data output pins. in the rgb mode, the green component is output. also, in the 16- bit or 24-bit yc mode, the y component is output. when 8-bit yc mode is selected, multiplexed pixel data is output. 19 199 114 281 20 115 282 21 vdb[7]/vdcx[7]/vdcb[7]/ avpp[39] vdb[6]/vdcx[6]/vdcb[6]/ avpp[38] vdb[5]/vdcx[5]/vdcb[5]/ avpp[37] vdb[4]/vdcx[4]/vdcb[4]/ avpp[36] vdb[3]/vdcx[3]/vdcb[3]/ avpp[35] vdb[2]/vdcx[2]/vdcb[2]/ avpp[34] vdb[1]/vdcx[1]/vdcb[1]/ avpp[33] vdb[0]/vdcx[0]/vdcb[0]/ avpp[32] input/ output ts yes b component output / c component output / c b component output / gpio these pins are display video data output pins. in the rgb mode, the blue component is out- put. in the 16-bit yc mode, the c b component and the c r component are time-shared and output. moreover, in the 24-bit yc mode, c b component is output. these pins are shared by gpio unit and set as gpio input setting af- ter reset. 200 vdhsync/vdhsync# output ts yes horizontal synchronous signal output this pin is for display synchronous signal out- put. its polarity is programmable. 116 vdvsync/vdvsync# output ts yes vertical synchronous signal output this pin is for display synchronous signal out- put. its polarity is programmable. 209 vdpclkin input ? yes display pixel clock input this pin inputs a basic clock to generate dis- play pixel clock output. 23 vdclkout output ts yes display pixel clock output pixel data is output in synchronization with this signal.
mb93423 21 (continued) pin no. pin name direction type bs description pfbga 117 enable/enable# output ts yes pixel output enable this signal shows that effective pixel data is output. its polarity is programmable. 123 topfield/topfield# output ts yes top field this pin shows that the top field is displayed. its polarity is programmable. 210 disable input ? yes video output disable when this signal is asserted, vdr[7 : 0] / vdcr[7 : 0], vdg[7 : 0] / vdy[7 : 0], vdb[7 : 0] / vdcx[7 : 0] / vdcb[7 : 0], vdhsync, vdvsync and vdclkout go in to the high impedanc e state. however, or- dinary operation continues inside.
mb93423 22 12. vcc pin no. pin name direction type bs description pfbga 7 191 103 268 8 269 104 192 vcr[7]/vccr[7]/avpp[15] vcr[6]/vccr[6]/avpp[14] vcr[5]/vccr[5]/avpp[13] vcr[4]/vccr[4]/avpp[12] vcr[3]/vccr[3]/avpp[11] vcr[2]/vccr[2]/avpp[10] vcr[1]/vccr[1]/avpp[9] vcr[0]/vccr[0]/avpp[8] input/ output ts yes r component input / c r component input / gpio these pins are capture video data input pins. in the rgb mode, the red component is input. in the 24-bit yc mode, c r compo- nent is input. these pins are shared by gpio and set as gpio input setting after re- set. 274 275 109 196 15 276 16 197 vcg[7]/vcy[7]/vcx[7] vcg[6]/vcy[6]/vcx[6] vcg[5]/vcy[5]/vcx[5] vcg[4]/vcy[4]/vcx[4] vcg[3]/vcy[3]/vcx[3] vcg[2]/vcy[2]/vcx[2] vcg[1]/vcy[1]/vcx[1] vcg[0]/vcy[0]/vcx[0] input ? yes g component input / y component input / yc multiplexed input these pins are capture video data input pins. in the rgb mode, the green compo- nent is input. also, in the 24-bit yc mode, the y component is input. when 8-bit yc mode is selected, multiplexed pixel data is output. 105 271 10 193 106 272 11 273 vcb[7]/vccx[7]/vccb[7]/ avpp[31] vcb[6]/vccx[6]/vccb[6]/ avpp[30] vcb[5]/vccx[5]/vccb[5]/ avpp[29] vcb[4]/vccx[4]/vccb[4]/ avpp[28] vcb[3]/vccx[3]/vccb[3]/ avpp[27 vcb[2]/vccx[2]/vccb[2]/ avpp[26] vcb[1]/vccx[1]/vccb[1]/ avpp[25] vcb[0]/vccx[0]/vccb[0]/ avpp[24] input/ output ts yes b component input / c component input / c b component input / gpio these pins are capture video data input pins. in the rgb mode, the blue component is input. also, in the 16-bit yc mode, c b component and c r component are time- shared and input. moreov er, in the 24-bit yc mode, c b component is input. these pins are shared by gpio unit and set as gpio in- put setting after reset. 107 vchsync/vchsync# input ? yes horizontal synchronous signal input this pin is a capture synchronous signal in- put pin. its polarity is programmable. 194 vcvsync/vcvsync# input ? yes vertical synchronous signal input this pin is a capture synchronous signal in- put pin. its polarity is programmable. 195 vcdclkin input ? yes capture pixel clock input this pin is a sampling clock for capture. the edge to use is programmable.
mb93423 23 13. audio 14. usb/usb-host pin no. pin name direction type bs description pfbga 211 sdo/dx output ts yes audio data output audio serial data is output. 125 lrcko/fs0 output sd yes lr clock output / ch0 synchronous signal when performing output that supports i 2 s or msb-justified, the lr clock is output. also , when performing output that supports the pcm highway, the ch0 synchronous signal (fs0) is output. 286 bcko/mclk output sd yes bit clock output this pin is an audio signal i/o bit clock output pin. i/o that supports the pcm highway always operates in the master mode. consequently, mclk th at is output by mb93423 is used for audio signal input. 30 sdi/dr input ? yes audio data input this pin is for audio serial data input. 32 lrcki/fs1 input/ output ts yes lr clock input / ch1 synchronous signal output when performing input that supports i 2 s or msb-justified, this pin becomes an lr clock input pin. also, when per- forming i/o that supports t he pcm highway, the ch1 syn- chronous signal (fs1) is output. 124 bcki input ? yes bit clock input this pin inputs bit clocks used for audio signal input that supports i 2 s or msb-justified. 284 fscki input ? yes basic clock input for audio output this pin inputs the basic clocks (256/384/512/756 fs) for generating bit clocks and lr clocks of audio signal output that supports i 2 s or msb-justified and for generating mclk, fs0, and fs1 of audio signal output that supports the pcm highway. pin no. pin name direction type bs description pfbga 215 udp input/ output ts no usb d + signal this pin is for differential signal ( + ) of usb function 292 udm input/ output ts no usb d ? s ignal this pin is for differential signal ( ? ) of usb function 131 uscki input ? yes usb clock input this pin inputs 48 mhz clock that is required by usb inter- face.
mb93423 24 15. i 2 c note : an i/o driver of i 2 c for mb93423 omits output through rate control. for this reason, the output through rate standard in the fast mode (400 kbps) of the i 2 c bus is not satisfied. since the standard for the stand ard mode (100 kbps) of the i 2 c bus is satisfied, it is connectable with the chip which is supporting sta ndard mode in the standard mode. if it is connection with the chip of standard mode down compatible, c onnection in the fast mode is also possible. pin no. pin name direction type bs description pfbga 287 126 scl[1] scl[0] input/ output od no i 2 c clock these pins are used for a clock signal of the i 2 c bus. scl[0] corresponds to i 2 c channel 0; scl[1] corresponds to i 2 c channel 1. 212 33 sda[1] sda[0] input/ output od no i 2 c data these pins are used for data signals for the i 2 c bus. sda[0] corresponds to i 2 c channel 0; sda[1] corresponds to i 2 c channel 1.
mb93423 25 16. ms pin no. pin name direction type bs description pfbga 289 xmscki input ? yes memory stick clock input [memory stick licensees] customers are advised to c onsult with our sales repre- sentatives, if you use ms interface. [non-licensees] this pin should be pulled up on a board. 213 msbs output sd yes memory stick bus state signal [memory stick licensees] customers are advised to c onsult with our sales repre- sentatives, if you use ms interface. [non-licensees] this pin should be open state on a board. 214 msclk output sd yes memory stick clock output [memory stick licensees] customers are advised to c onsult with our sales repre- sentatives, if you use ms interface. [non-licensees] this pin should be open state on a board. 128 msdio/msdio[0] input/ output pd yes memory stick serial data signal [memory stick licensees] customers are advised to c onsult with our sales repre- sentatives, if you use ms interface. [non-licensees] this pin should be open state on a board. 291 35 290 msdio[3] msdio[2] msdio[1] input/ output pd yes memory stick serial data signal [memory stick licensees] customers are advised to c onsult with our sales repre- sentatives, if you use ms interface. [non-licensees] these pins should be open state on a board. 34 msins input ? yes memory stick insert detection signal [memory stick licensees] customers are advised to c onsult with our sales repre- sentatives, if you use ms interface. [non-licensees] this pin should be open state on a board.
mb93423 26 pin state initial value : indicates pin state immediately after power-on reset. the meaning of each symbol is given below : (continued) symbol meaning h indicates high level l indicates low level hiz indicates high-impedance state x indicates either high level or low level pin name initial state core sleep mode bus sleep mode pll operation mode pll stop mode a[23 : 2] hiz operation x x x d[31 : 16] hiz operation hiz hiz hiz be[0 : 3]/be#[0 : 3] hiz operation x x x bs# , rd# , we# hiz operation h h h dir hiz operation x x x rdy# ? operation hiz hiz hiz err# ??? ? ? cs#[3 : 0] h operation h h h dcs#[3 : 0] h operation l l l dba[1 : 0] l operation x x x da[12 : 0] x operation x x x dras# , dcas# h operation l l l dwe# h operation h h h dcke h operation l l l ddqm[0 : 3] h operation h h h ddq[31 : 0] hiz operation hiz hiz hiz dclk l operation operation operation l dclkfb ??? ? ? irq#[0 : 3]/pp[0 : 3] hiz operation operation x or hiz x or hiz tout[0]/gate[0]/pp[4] hiz operation operation x or hiz x or hiz tout[1]/gate[1]/pp[5] hiz operation operation x or hiz x or hiz rxd[0]/pp[6] hiz operation operation x or hiz x or hiz txd[0]/pp[7] hiz operation operation x or hiz x or hiz msdirs#/pp[8] hiz operation x or hiz x or hiz x or hiz msdirp#/pp[9] hiz operation x or hiz x or hiz x or hiz rxd[1]/pp[10] hiz operation operation x or hiz x or hiz txd[1]/pp[11] hiz operation operation x or hiz x or hiz
mb93423 27 (continued) pin name initial state core sleep mode bus sleep mode pll operation mode pll stop mode dreq#[0]/pp[12] hiz operation x or hiz x or hiz x or hiz dreq#[1]/pp[15] hiz operation x or hiz x or hiz x or hiz dreq#[2]/pp[18] hiz operation x or hiz x or hiz x or hiz dreq#[3]/pp[19] hiz operation x or hiz x or hiz x or hiz erst# , hrst# ??? ? ? ecv ??? ? ? ed hiz hiz hiz hiz hiz eclk lll l l prst# ??? ? ? rstout# l operation operation operation operation ramboot# ??? ? ? cpuhold l x x x x clkin ??? ? ? cmode[3 : 0] ??? ? ? tdi ??? ? ? tdo hiz hiz hiz hiz hiz tms , tck , trst# ??? ? ? testmode , tdc , mtestmode ??? ? ? vdr[7 : 0]/vdcr[7 : 0]/ avpp[23 : 16] ? operation x or hiz x or hiz x or hiz vdg[7 : 0]/vdy[7 : 0]/vdx[7 : 0] ? operation x x x vdb[7 : 0]/vdcx[7 : 0]/ vdcb[7 : 0]/avpp[39 : 32] ? operation x or hiz x or hiz x or hiz vdhsync/vdhsync# ? operation x x x vdvsync/vdvsync# ? operation x x x vdpclkin ??? ? ? vdclkout ? operation operation operation operation enable/enable# ? operation x x x topfield/topfield# ? operation x x x disable ??? ? ? vcr[7 : 0]/vccr[7 : 0]/ avpp[15 : 8] ? operation x or hiz x or hiz x or hiz vcg[7 : 0]/vcy[7 : 0]/vcx[7 : 0] ??? ? ? vcb[7 : 0]/vccx[7 : 0]/ vccb[7 : 0]/avpp[31 : 24] ? operation x or hiz x or hiz x or hiz
mb93423 28 (continued) pin name initial state core sleep mode bus sleep mode pll operation mode pll stop mode vchsync/vchsync# ??? ? ? vcvsync/vcvsync# ??? ? ? vcdclkin ??? ? ? sdo/dx ? operation x x x lrcko/fs0 ? operation operation operation operation bcko/mclk ? operation operation operation operation sdi/dr ??? ? ? lrcki/fs1 ? operation x or hiz x or hiz x or hiz bcki ??? ? ? fscki ??? ? ? udp ? operation hiz hiz hiz udm ? operation hiz hiz hiz uscki ??? ? ? scl[1 : 0] ? hiz hiz hiz hiz sda[1 : 0] ? hiz hiz hiz hiz xmscki ??? ? ? msbs ? operation x or hiz x or hiz x or hiz msclk ? operation operation operation operation msdio/msdio[0] ? operation x or hiz x or hiz x or hiz msdio[3 : 1] ? operation x or hiz x or hiz x or hiz msins ??? ? ?
mb93423 29 handling devices ? preventing latch-up mb93423 may suffer latch-up under the following conditions : ? a voltage higher than v de or lower than v ss is applied to an input or output pin. ? a voltage higher than the rated voltage is applied between vde pin and vss pin. latch-up may increase the power supply current dr astically, causing thermal damage to the device. for the same reason, care must also be taken in not allowing the anal og power-supply voltage (v dd ) to exceed the digital power-supply voltage. ? handling unused pins leaving unused input pins open may result in misbeha vior or latch up and possible permanent damage of the device. therefore they must be pulled up or pulled down through resistors. in this case those resistors should be more than 2 k ? . unused bi-directional pins should be set to the output st ate and can be left open, or the input state with the above described connection. ? power supply pins in products with multiple vde, vdd or vss pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. however you must connect the pins to an external power and a ground line to lower the electro-magnetic emissi on level to prevent abnormal operation of strobe signals caused by the rise in the ground level, a nd to conform to the total current rating. make sure to connect vde, vdd and vss pins via the lowest impedance to power lines. it is recommended to provide a bypass capacitor of around 0.1 f between vde, vdd and vss pins near the device. ? pull-up/down resistors the mb93423 does not support internal pull-up/down resi stors (except pu/pd pin type) . use external compo- nents where needed. ? n.c. pin the n.c. (internally connected) pin must be opened for use.
mb93423 30 block diagram low-bandwidth peripheral bus (32-bit) interrupt controller (8 ext. sources+ 11 intl. sources) gpio (16-bit) timer (3 channels) uart (2 channels) bus bridge c-unit debug support unit dmac (4 channels) local bus interface sdramc av peripheral controller 32-bit address 32-bit data 32-bit data 32-bit address 32-bit address 32-bit inst. address 32-bit address 32-bit data 32-bit data 32-bit address 32-bit data 32-bit data 32-bit data address 32-bit address 32-bit data 32-bit data 32-bit address 32-bit data 32-bit data high-bandwidth system interconnect (32-bit) on-chip bus interface fr400 core 64-bit instruction 64-bit data 64-bit data data cache (8k bytes) memory protection instruction cache (8k bytes) strage unit 64-bit instruction 64-bit data 64-bit data 64-bit data 64-bit data 64-bit data 64-bit data instruction fetch interrupt control integer-unit pipe-line control branch control gr (32 bits 32 words) fr (32 bits 32 words) media-unit 32-bit address 32-bit data 32-bit data
mb93423 31 electric characteristics 1. absolute maximum ratings * : the parameter is based on v ss = 0 v. warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. 2. recommended operating conditions (v ss = 0 v) parameter symbol rating unit min max power supply voltage (external) * v de v ss ? 0.5 v ss + 4.0 v power supply voltage (internal) * v dd v ss ? 0.5 v ss + 2.5 v power supply voltage (pll) * v ddp v ss ? 0.5 v ss + 2.5 v input voltage* v i v ss ? 0.5 v de + 0.5 ( 4.0) v storage temperature t stg ? 55 + 125 c parameter symbol value unit min typ max power supply voltage (external) v de 240 mhz 3.15 3.3 3.45 v 266 mhz 3.15 3.3 3.45 v power supply voltage (internal) v dd 240 mhz 1.7 1.8 1.9 v 266 mhz 1.7 1.8 1.9 v power supply voltage (pll) v ddp 240 mhz 1.7 1.8 1.9 v 266 mhz 1.7 1.8 1.9 v ?l? level input voltage v il ? 0.3 ? 0.8 v ?h? level input voltage v ih 2.0 ? v de + 0.3 v operating temperature ta 0 + 25 + 70 c
mb93423 32 usb (v ss = 0 v) * : it is necessary to attach ?rpu? outside. notes on board wiring for connecting the power supply and ground (gnd) , use multiple vdd and vss pins. the system board based on the mb93423 must be a multi-layer board containing power supply (v dd ) and gnd (v ss ) layers for stable power supply. insert sufficient decoupling capacitors (condensers) near the mb93423. changes to the output levels of many of the output pins on the mb93423 (i n particular, those with large load capacitance) may cause variation in power supply. for those systems which run at a high frequency, lo w-inductance capacitors and mutual wiring are recom- mended. inductance can be lowered by shortening the distance between the processor and decoupling ca- pacitor warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit min typ max ?h? level input voltage v ihu 2.0 ?? v ?l? level input voltage v ilu ?? 0.8 v differential input sensitivity v diu 0.2 ?? v differential common mode range v cmu 0.8 ? 2.5 v ?h? level output voltage v ohu 2.8 ? 3.45 v ?l? level output voltage v olu 0.0 ? 0.3 v output signal crossover voltage v crsu 1.3 ? 2.0 v bus pull-up/down resistor on upstream port rpu* 1.425 ? 1.575 k ? termination voltage on upstream port pull-up v term 3.15 ? 3.45 v
mb93423 33 3. dc characteristics (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) parameter symbol condition value unit min typ max ?l? level input voltage v il ? 0 ? 0.8 v ?h? level input voltage v ih ? 2.0 ? v de v ?l? level output voltage v ol i ol = 2 ma 0 ? 0.4 v ?h? level output voltage v oh i oh = ? 2 ma v de ? 0.4 ? v de v input leakage current i li v in = 0 or v de ? 5 ? 5 a tri-state output leakage current i lz v out = 0 or v de ? 5 ? 5 a power supply current (v de ) i de 240 mhz cmode = 0x9, clkin = 60 mhz, (dhrystone2.1) no load 02040ma 266 mhz cmode = 0x9, clkin = 66 mhz, (dhrystone2.1) no load 02244ma power supply current (v dd ) i dd 240 mhz cmode = 0x9, clkin = 60 mhz, (dhrystone2.1) ? 300 360 ma 266 mhz cmode = 0x9, clkin = 66 mhz, (dhrystone2.1) ? 310 360 ma power supply current (v ddp ) i ddp 240 mhz cmode = 0x9, clkin = 60 mhz, (dhrystone2.1) ? 36ma 266 mhz cmode = 0x9, clkin = 66 mhz, (dhrystone2.1) ? 36ma at sleep power supply current i coresleep 240 mhz core sleep mode, clkin = 60 mhz ? 40 ? ma 266 mhz core sleep mode, clkin = 66 mhz ? 40 ? ma i bussleep 240 mhz bus sleep mode, clkin = 60 mhz ? 25 ? ma 266 mhz bus sleep mode, clkin = 66 mhz ? 25 ? ma i pllon 240 mhz pll on mode, clkin = 60 mhz ? 12 ? ma 266 mhz pll on mode, clkin = 66 mhz ? 12 ? ma i plloff pll stop mode, clkin = 0 mhz ? 0.5 ? ma capacity of pins c pin v de = v i = 0, f = 1 mhz ?? 16 pf
mb93423 34 usb (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) parameter symbol conditions value unit min typ max ?l? level output voltage v ol i ol = 20 ma 0 ? 0.4 v ?h? level output voltage v oh i oh = ? 20 ma v de ? 0.5 ? v de v ?l? level output current i ol v ol = 0.4 v 20 ?? ma ?h? level output current i oh v oh = v de ? 0.4 v ? 20 ?? ma output short-circuit current i os ??? 300 ma
mb93423 35 4. ac characteristics (1) local bus interface (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) * : refer to ?5. clock setting? for details. (continued) item parameter reference signal 240 mhz 266 mhz unit min max min max clkin input clkin period (t clkin ) ? 16.7* 30* 15* 30* ns clkin high time ? 6.0 ? 6.0 ? ns clkin low time ? 6.0 ? 6.0 ? ns clkin rise time ?? 1.0 ? 1.0 ns clkin fall time ?? 1.0 ? 1.0 ns local-bus i/f output a [23 : 2] output valid delay time clkin rise 1.5 6.0 1.5 6.0 ns output hold time clkin rise 1.5 ? 1.5 ? ns d [31 : 16] output valid delay time clkin rise 1.5 6.0 1.5 6.0 ns output hold time clkin rise 1.5 ? 1.5 ? ns be/be# [0 : 3] output valid delay time clkin rise 1.5 6.0 1.5 6.0 ns output hold time clkin rise 1.5 ? 1.5 ? ns bs# output valid delay time clkin rise 1.5 6.0 1.5 6.0 ns output hold time clkin rise 1.5 ? 1.5 ? ns rd# output valid delay time clkin rise 1.5 6.0 1.5 6.0 ns output hold time clkin rise 1.5 ? 1.5 ? ns we# output valid delay time clkin fall 1.0 7.0 1.0 7.0 ns output hold time clkin fall 1.0 ? 1.0 ? ns dir output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns output hold time clkin rise 1.5 ? 1.5 ? ns rdy# output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns output hold time clkin rise 1.5 ? 1.5 ? ns cs# [3 : 0] output valid delay time clkin rise 1.5 6.5 1.5 6.5 ns output hold time clkin rise 1.5 ? 1.5 ? ns local-bus i/f input a [23 : 2] input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns d [31 : 16] input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns be/be# [0 : 3] input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns bs# input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns
mb93423 36 (continued) (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) note : each parameter is valid within the specified rang es of temperatures and supply voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, the input level is 0.4 v to 2.4 v, and t he input rise time and fall time are 1.5 ns or less. the external output load capacitance is 30 pf. item parameter reference signal 240 mhz 266 mhz unit min max min max local-bus i/f input dir input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns rdy# input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns err# input setup time clkin rise 3.0 ? 3.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns c lkin i nput pin o utput pin i nput and o utput pin w e# setup hold hold hold valid valid
mb93423 37 (2) sdram interface (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) * : this value is decided by cmode. notes: ? each parameter is valid within the specified ran ges of temperatures and supply voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v, the input level is 0.4 v to 2.4 v, and the input rise time and fall time are 1.5 ns or less unless otherwise noted. the external output load capacitanc e is 30 pf unless otherwise noted. ? the frequency of the input to dclkfb and the output from dclk is decided by the input frequency to clkin, and setup of a cmode [3 : 0] pins . refer to ?5. clock setting? for details. item parameter reference signal 240 mhz 266 mhz unit minmaxminmax dclkfb input dclkfb period (t dclkfb ) ? 8.3* 15* 7.5* 15* ns dclkfb high time ? 2.5 ? 2.5 ? ns dclkfb low time ? 2.5 ? 2.5 ? ns dclkfb rise time ?? 1.0 ? 1.0 ns dclkfb fall time ?? 1.0 ? 1.0 ns sdram i/f output dcs# [3 : 0] output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns dba [1 : 0] output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns da [12 : 0] output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns dras# output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns dcas# output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns dwe# output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns dcke output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns ddqm [0 : 3] output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns ddq [31 : 0] output valid delay time dclkfb rise 1.0 4.5 1.0 4.5 ns output hold time dclkfb rise 1.0 ? 1.0 ? ns sdram i/f input ddq [31 : 0] input setup time dclkfb rise 1.0 ? 1.0 ? ns input hold time dclkfb rise 1.0 ? 1.0 ? ns setup hold hold valid d clkfb o utput pin i nput and o utput pin
mb93423 38 ? this lsi outputs dclk which is supplied to sdram as a clock. pll is built into this lsi. adjust the phase of dclk so that the clk pi n of sdram and the internal phase in this lsi may be nearly equal. therefore, when connecting, adjust the delay time of the feedback path from dclk to dclkfb, so that the phase of the clock input to dclk fb which is the feedback signal to pll, and the phase of the clock (wave shape on the reception edge of dclk) i nput to clk of sdram may be nearly equal.
mb93423 39 (3) general peripheral resources (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) (continued) item parameter reference signal 240 mhz 266 mhz unit min max min max resources output irq# [0 : 3]/ pp [0 : 3] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns tout[0]/ gate[0]/ pp[4] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns tout[1]/ gate[1]/ pp[5] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns rxd[0]/pp[6] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns txd[0]/pp[7] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns msdirs#/ pp[8] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns msdirp#/ pp[9] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns rxd[1]/pp[10] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns txd[1]/pp[11] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns dreq# [0]/ pp[12] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns dreq# [1]/ pp[15] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns dreq#[2]/ pp[18] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns dreq#[3]/ pp[19] output valid delay time clkin rise 2.0 10.0 2.0 10.0 ns output hold time clkin rise 2.0 ? 2.0 ? ns resources input irq#[0 : 3] / pp [0 : 3] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns tout[0]/ gate[0]/ pp[4] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns tout[1]/ gate[1]/ pp[5] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns
mb93423 40 (continued) (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) note : each parameter is valid within the specified rang es of temperatures and supply voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0 v) level. the timing measurement reference point is 1.5 v, the input level is 0.4 v to 2.4 v, and the input rise time and fall time are 1.5 ns or less. the external output load capacit ance is 30 pf unless otherwise noted. item parameter reference signal 240 mhz 266 mhz unit minmaxminmax resources input rxd[0]/pp[6] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns txd[0]/pp[7] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns msdirs#/ pp[8] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns msdirp#/ pp[9] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns rxd[1]/pp[10] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns txd[1]/pp[11] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dreq#[0]/ pp[12] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dreq#[1]/ pp[15] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dreq#[2]/ pp[18] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns dreq#[3]/ pp[19] input setup time clkin rise 4.0 ? 4.0 ? ns input hold time clkin rise 1.5 ? 1.5 ? ns c lkin i nput pin o utput pin i nput and o utput pin setup hold hold valid
mb93423 41 (4) ice interface (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) note : each parameter is valid within the specified rang es of temperatures and supply voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v and the input level is 0.4 v to 2.4 v. the input ri se time and fall time are 1.5 ns or less. the external output load capacitance is 30 pf unless otherwise noted. item parameter reference signal 240 mhz 266 mhz unit min max min max eclk output eclk output period ? 30 ? 30 ? ns eclk output high time ? 13.0 ? 13.0 ? ns eclk output low time ? 13.0 ? 13.0 ? ns eclk output rise time ?? 2.0 ? 2.0 ns eclk output fall time ?? 2.0 ? 2.0 ns ice output ed output valid delay time eclk rise ? 8.0 ? 8.0 ns output hold time eclk rise 0.0 ? 0.0 ? ns ice input erst# input setup time eclk rise 5.0 ? 5.0 ? ns input hold time eclk rise 0.0 ? 0.0 ? ns hrst# low pulse width ? 16 ? 16 ? t clkin ecv input setup time eclk rise 5.0 ? 5.0 ? ns input hold time eclk rise 0.0 ? 0.0 ? ns ed input setup time eclk rise 5.0 ? 5.0 ? ns input hold time eclk rise 0.0 ? 0.0 ? ns e clk i nput pin i nput and o utput pin setup hold hold valid
mb93423 42 (5) reset (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) (6) cpu status (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) (7) clocks (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) (8) test (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) item parameter reference signal 240 mhz 266 mhz unit min max min max reset output rstout# output valid delay time clkin rise 0 8.0 0 8.0 ns reset input prst# low pulse width ? 16 ? 16 ? t clkin boot input ramboot# low pulse width ? 16 ? 16 ? t clkin item parameter reference signal 240 mhz 266 mhz unit min max min max cpu output cpuhold output valid delay time clkin rise 0 8.0 0 8.0 ns item parameter reference signal 240 mhz 266 mhz unit min max min max clock mode input cmode[3 : 0] input setup time ? must be fixed to ?h? or ?l? ? input hold time ? must be fixed to ?h? or ?l? ? item parameter reference signal 240 mhz 266 mhz unit min max min max test mode input testmode input setup time ? must be fixed to ?l? ? input hold time ? must be fixed to ?l? ? tdc input setup time ? must be fixed to ?l? ? input hold time ? must be fixed to ?l? ? mtestmode input setup time ? must be fixed to ?l? ? input hold time ? must be fixed to ?l? ?
mb93423 43 (9) video display controller (vdc) (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) * : the falling edge of vdclkout is synchronous with respect to the rising edge of vdpclkin. note : each parameter is valid within the specified rang es of temperatures and supp ly voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v and the input level is 0.4 v to 2.4 v. the external output load capacitance is 30 pf. item parameter reference signal 240 mhz/266 mhz unit min max vdc clock input vdpclkin period ? 12.5 50 ns vdpclkin high time ? 4.0 ? ns vdpclkin low time ? 4.0 ? ns vdc i/f output vdr [7 : 0]/vdcr [7 : 0] output valid delay time vdclkout fall ? 2.0 3.0 ns output hold time ??? ns vdg [7 : 0]/vdy [7 : 0]/ vdx[7 : 0] output valid delay time vdclkout fall ? 2.0 3.0 ns vdb [7 : 0]/vdcx[7 : 0]/ vdcb [7 : 0] output valid delay time vdclkout fall ? 2.0 3.0 ns output hold time ??? ns vdhsync/vdhsync# output valid delay time vdclkout fall ? 2.0 3.0 ns vdvsync/vdvsync# output valid delay time vdclkout fall ? 2.0 3.0 ns enable/enable# output valid delay time vdclkout fall ? 2.0 3.0 ns topfield/ topfield# output valid delay time vdclkout fall ? 2.0 3.0 ns vdclkout* output valid delay time vdpclkin rise 7.0 14.0 ns vdc i/f input disable input setup time vdpclkin rise 2.5 ? ns input hold time vdpclkin rise 1.5 ? ns
mb93423 44 (10) video capture controller (vcc) (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) note : each parameter is valid within the specified rang es of temperatures and supply voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v and the input level is 0.4 v to 2.4 v. the external output load capacitance is 30 pf. item parameter reference signal 240 mhz/266 mhz unit min max vcc clock input vcdclkin period ? 12.5 125 ns vcdclkin high time ? 4 ? ns vcdclkin low time ? 4 ? ns vcc i/f input vcr [7 : 0]/vccr [7 : 0] input setup time vcdclkin rise 2.5 ? ns input hold time vcdclkin rise 1.5 ? ns vcg[7 : 0]/vcy[7 : 0]/ vcx[7 : 0] input setup time vcdclkin rise 2.5 ? ns input hold time vcdclkin rise 1.5 ? ns vcb[7 : 0]/vccx[7 : 0]/ vccb[7 : 0] input setup time vcdclkin rise 2.5 ? ns input hold time vcdclkin rise 1.5 ? ns vchsync/vchsync# input setup time vcdclkin rise 2.5 ? ns input hold time vcdclkin rise 1.5 ? ns vcvsync/vcvsync# input setup time vcdclkin rise 2.5 ? ns input hold time vcdclkin rise 1.5 ? ns
mb93423 45 (11) audio (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) * : lrcko and sdo signals are generated with respect to the falling edge of bcko (duty 50 % ) . note : each parameter is valid within the specified rang es of temperatures and supply voltages unless otherwise noted. each voltage value is based on the gnd (v ss = 0.0 v) level. the timing measurement reference point is 1.5 v and the input level is 0.4 v to 2.4 v. the external output load capacitance is 30 pf. item parameter reference signal 240 mhz/266 mhz unit min max audio clock input fscki period ? 25 ? ns fscki high time ? 10.5 ? ns fscki low time ? 10.5 ? ns bcki period ? 312.5 ? ns bcki high time ? 130 ? ns bcki low time ? 130 ? ns audio i/f output sdo* output valid delay time fscki rise 3.0 10.0 ns lrcko* output valid delay time fscki rise 3.0 10.0 ns bcko* output valid delay time fscki rise 3.0 10.0 ns lrcki output valid delay time fscki rise 3.0 10.0 ns audio i/f input sdi input setup time bcki rise 50 ? ns input hold time bcki rise 50 ? ns lrcki input setup time bcki rise 50 ? ns input hold time bcki rise 50 ? ns
mb93423 46 (12) usb interface (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) notes: ? frequency of uscki is set to 48 mhz in order to carry out operation based on the standard of usb 2.0 fs. and it is necessary to put in a cloc k with a frequency accuracy of 2500 ppm. ? in order to fulfill the standard of usb 2. 0 fs, it is necessary to add 25 to 30 ? in-series resistance outside. (13) i 2 c (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) * : 20 + 0.1 c (c = capacitance of one bus line in pf) notes: ? each parameter is valid within the specified r anges of temperatures and supply voltages unless otherwise noted. ? each voltage value is based on the gnd level. t he timing measurement reference point is 1.5 v and the input level is 0.4 v to 2.4 v, and the input rise time and fall time are 1.5 ns or less. ? the external output l oad capacitance is 30 pf. item parameter reference signal 240 mhz/266 mhz unit min max usb clock input uscki period ? 20 ? ns uscki high time ? 8 ? ns uscki low time ? 8 ? ns usb driver d + /d ? rise time t fr ? 420ns d + /d ? fall time t ff ? 420ns differential rise and fall time matching ? 90 111.11 % driver output resistance ? 319 ? item parameter reference signal 240 mhz/266 mhz unit min max i 2 c i/f output scl[1 : 0] output fall time ? 23* 250 ns output rise time ? 23* 300 ns sda[1 : 0] output fall time ? 23* 1000 ns output rise time ? 23* 300 ns d + 90% t fr t ff 10% 10% 90% d ?
mb93423 47 (14) memory stick interface customers are advised to consult with our sale s representatives , if you use ms interface. (15) power sequence (v de = 3.3 v 0.15 v, v dd = v ddp = 1.8 v 0.1 v, v ss = 0 v, ta = 0 c to + 70 c) note : power-off sequence is not defined. item parameter reference signal 240 mhz/266 mhz unit min max power-on v de rise time t re ?? 30 ms v dd rise time t rd ?? 20 ms delay time from v de rise to v dd rise t dred ?? 100 100 ms v de ? min v dd ? min v de v dd t re t rd t dred power-on sequence
mb93423 48 5. clock setting in this lsi, the clock signal inputted into clkin is multiplied by internal pl l, and it has distributed to each part in lsi. the multiplication rate for each clock is decided using th e cmode [3 : 0] pins. depending on this setup, the maximum frequency of clkin may be restricted. the maximum frequency that can be inputted into clkin and the frequency of each par t of lsi are shown below. * : ? ? indicates the frequency ratio for the external input clock. notes : ? as the setting of cmode = 0, 1, 2, 3, 6, 7, a, e, f is not conf irmed for operation guarantee, do not set them. ? by default, the operating frequency of the resource bu s clock is the same as that of the external bus. when clkc.p0 is set to ?1?, the operating frequency of the resource bus clock is half that of the external bus. cmode [0]to[3] ratio* clkin frequency internal operating clock of this lsi 3 2 1 0 frequency external bus sdram core bus core dsu 00 - - reserved 0100 ratio* 1 1 1 2 2 0.25 freq. [mhz] mb93423bgl-ge1 60.0 60.0 60.0 120.0 120.0 15.0 MB93423-26BGL-GE1 66.7 66.7 66.7 133.3 133.3 16.7 0101 ratio* 1 1 2 4 4 0.5 freq. [mhz] mb93423bgl-ge1 30.0 30.0 60.0 120.0 120.0 15.0 MB93423-26BGL-GE1 33.3 33.3 66.7 133.3 133.3 16.7 011 - reserved 1000 ratio* 1 1 1 1 2 0.25 freq. [mhz] mb93423bgl-ge1 60.0 60.0 60.0 60.0 120.0 15.0 MB93423-26BGL-GE1 66.7 66.7 66.7 66.7 133.3 16.7 1001 ratio* 1 1 2 2 4 0.5 freq. [mhz] mb93423bgl-ge1 60.0 60.0 120.0 120.0 240.0 30.0 MB93423-26BGL-GE1 66.7 66.7 133.3 133.3 266.6 33.3 1010 reserved 1011 ratio* 1 1 4 4 8 1 freq. [mhz] mb93423bgl-ge1 30.0 30.0 120.0 120.0 240.0 30.0 MB93423-26BGL-GE1 33.3 33.3 133.3 133.3 266.6 33.3 1100 ratio* 1 1 1 2 4 0.5 freq. [mhz] mb93423bgl-ge1 60.0 60.0 60.0 60.0 240.0 30.0 MB93423-26BGL-GE1 66.7 66.7 66.7 66.7 266.6 33.3 1101 ratio* 1 1 2 4 8 1 freq. [mhz] mb93423bgl-ge1 30.0 30.0 60.0 120.0 240.0 30.0 MB93423-26BGL-GE1 33.3 33.3 66.7 133.3 266.6 33.3 111 - reserved
mb93423 49 connection with memory 1. connection with rom or sram an example of connection between this proc essor and rom or sram, etc. is shown below. connection example : when connecting 2 srams (256 k 8 bits each) to 16-bit bus (the polarity of be is positive logic.) sram (1) a [17:0] i/o [7:0] oe# we# cs1# cs2 sram (2) a [17:0] i/o [7:0] oe# we# cs1# cs2 pull-down in this connection example mb93423 a [19:2] cs# [n] dir we# be [0] be [1] d [31:24] d [23:16] rdy# pull-up in this connection example
mb93423 50 2. connection with sdram dcs#[2] and dcs#[3] are only used for connecting the 1 68-pin registered dimm. connect the 168-pin registered dimm as follows. the dimm must be ?registered?. in the registered dimm, it is assumed that the module connected to dcs#[2] or dcs#[3] is used after dc s#, dba, da, dras#, dcas#, dwe#, ddqm, and dcke are latched once at the rising of dclk signal. when using dcs#[2] or dc s#[3], the bus width must be set to the 32-bit mode. mb93423 dba [1:0] dcas# dcs# [2] dras# dwe# da [12:0] ddq [31:16] 168 pins registered-dimm ba [1:0] a [12:0] s0# ras# cas# we# dqmb [5:4] cke clk ddqm [0:1] dcke dclk dclkfb ddq [15:0] ddqm [2:3] dqmb [7:6] dqmb [1:0] dqmb [3:2] dq [47:32] dq [63:48] dq [15:0] dq [31:16] s2# dcs# [3]
mb93423 51 example : connecting registered-dimm to dcs#[3 : 2] dcs#[2] and dcs#[3] are only used for connecting the 1 68-pin registered dimm. connect the 168-pin registered dimm as follows. the dimm must be ?registered?. in the registered dimm, it is assumed that the module connected to dcs#[2] or dcs#[3] is used after dc s#, dba, da, dras#, dcas#, dwe#, ddqm, and dcke are latched once at the rising of dclk signal. when using dcs#[2] or dc s#[3], the bus width must be set to the 32-bit mode. mb93423 dba [1:0] dcas# dcs# [2] dras# dwe# da [12:0] ddq [31:16] 168 pins registered-dimm ba [1:0] a [12:0] s0# ras# cas# we# dqmb [5:4] cke clk ddqm [0:1] dcke dclk dclkfb ddq [15:0] ddqm [2:3] dqmb [7:6] dqmb [1:0] dqmb [3:2] dq [47:32] dq [63:48] dq [15:0] dq [31:16] s2# dcs# [3]
mb93423 52 connection with peripheral device 1. connection with mb93443 (ide/pc-card host controller) an example of connection between this processo r and peripheral device is shown below 16-bit bus. clock gen. mb93423 clkin d [31 : 16] a [15 : 2] be [0 :3 ] dir bs# rdy# dreq# [n] ( n : 0 to 3 ) cs# [n] ( n : arbitrary except 0 ) irq [n] / pp [n] ( n : 0 to 3 ) prst# clkin d [31 : 16] d [15 : 00] a [15 : 2] be [0 :3 ] dir bs# rdy# dreq# csc# csr# irq# bstreq# bstack# prst# bw16 mb93443 pull - up is required. pull - up is required. correspondence is arbitrary. correspondence is arbitrary. correspondence is arbitrary. reset gen.
mb93423 53 2. connection with mb93441 (pci bridge chip) an example of connection between this processo r and peripheral device is shown below 16-bit bus. note : because address a[23 : 16] is connected to gnd as shown in the above figure, it will be short out when mb93441 is a bus master. however, there is no bus slave function and it is prohibi ted to be a bus master, therefore it will not be short out. clock gen. mb93423 clkin d [31 : 16] a [15 : 2] be [0 :3 ] dir bs# rdy# dreq [n] # ( n : 0 to 3 ) cs [n] # ( n : arbitrary except 0 ) irq [n] / pp [n] ( n : 0 to 3 ) prst# clkin breq# open d [31 : 16] d [15 : 0] a [23 : 16] bgnt# a [15 : 2] be [0 :3 ] dir bs# rdy# dreq# csc# csr# irq# bstreq# bstack# prst# bw16 mb93441 pull - up is required. pull - up is required. correspondence is arbitrary. correspondence is arbitrary. correspondence is arbitrary. reset gen.
mb93423 54 package dimension 337-ball plastic pfbga (bga-337p-m03) c 2005 fujitsu limited b337003s-c-1-1 13.00 0.10(.512 .004) 12.00(.472) 0.50(.020) typ 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae (index area) s 0.10(.004) 1.15 0.20 s (seated height) (.045 .008) (.010 .004) (stand off) 0.25 0.10 s b 0.20(.008) s a 0.20(.008) 13.00 0.10 (.512 .004) ? 0.05(.002) b a s m 386- ? 0.30 0.10 (386- ? .012 .004) ref a 0.50(.020) typ 12.00(.472)ref b 3.00(.118) ref ref 3.00(.118) index dimensions in mm (inches). note: the values in parent heses are refe rence values.
mb93423 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0505 ? 2005 fujitsu limited printed in japan

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